A differential receiver responds to the difference between two signals, but both conductors still interact with their reference environment. A good pair therefore requires more than equal trace lengths. Maintain a deliberate geometry, control asymmetry at transitions and verify the complete channel using the interface and device requirements.
Define the pair rules from the interface
Record the required differential impedance, allowable intra-pair skew, loss and topology. Separate these requirements from any matching between different lanes. A rule for one protocol or device generation should not automatically become a board-wide rule for every differential net.
Keep geometry consistent where it matters
Trace width, pair spacing, reference distance and nearby copper affect the field distribution. Short neck-downs at pads may be necessary, but their length and symmetry should be intentional. Review the connector escape and package breakout before assuming that a long straight section determines the whole channel.
Treat length as a proxy for delay
Equal CAD length does not always imply equal electrical delay. Different layers, glass reinforcement, bends and dissimilar transitions can contribute to skew. Add tuning only where it solves a documented mismatch, and leave enough separation between tuning segments to avoid creating an unmodeled coupled structure.
Inspect mode conversion and return paths
An asymmetric via field or plane interruption can convert part of the intended differential signal into common-mode energy. Review the reference path for each transition and the symmetry of nearby conductors. Differential signaling does not make reference discontinuities irrelevant.
Example: matching the wrong quantity
Two routes report the same physical length, but one leg uses an extra via and a different layer for a short section. Before adding more serpentine, compare the electrical delay and discontinuities of both legs. The useful correction may be matching the topology instead of matching the displayed length more tightly.
Design review checklist
- Identify each pair and its applicable interface limits.
- Inspect pad escapes, connector pin fields and via count symmetry.
- Review tuning in the extracted channel, not only the length report.
- Keep pair constraints with the released stack-up.