Follow the current return path
A signal and its return current form a circuit. Plane gaps, reference changes and connector transitions can increase loop area and disturb the interconnect. Review these transitions instead of checking trace length alone.
Use the relevant time scale
Fast edge rates can make an interconnect electrically long even when the clock frequency is modest. Evaluate propagation delay, termination and discontinuities against the actual device behavior.
Validate with the right model
Use models appropriate to the channel, packages, connectors and vias. State assumptions and compare simulation or measurement with defined acceptance criteria. A nominal impedance target is only one part of the complete channel budget.
Prepare the review package
- Interface requirements and rise/fall times
- Stack-up and routing geometry
- Driver, receiver and connector models
- Measurement or simulation acceptance criteria